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Paper details
Number 1 - March 2024
Volume 34 - 2024
Reducing the number of LUTs for Mealy FSMs with state transformation
Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek
Abstract
In many digital systems, various sequential blocks are used. This paper is devoted to the case where the model of a Mealy
finite state machine (FSM) represents the behaviour of a sequential block. The chip area occupied by an FSMcircuit is one
of the most important characteristics used in logic synthesis. In this paper, a method is proposed which aims at reducing
LUT counts for FPGA-based Mealy FSMs with transformation of state codes into FSM outputs. This is done using the
combined state codes. Such an approach allows excluding a block of transformation of binary state codes into extended
state codes. The proposed method leads to LUT-based Mealy FSM circuits having exactly three levels of logic blocks.
Under certain conditions, each function for any logic level is represented by a circuit including a single LUT. The proposed
approach is illustrated with an example of synthesis. The results of experiments conducted using standard benchmarks
show that the proposed method produces LUT-based FSM circuits with significantly smaller LUT counts than is the case
for circuits produced by other investigated methods (Auto and One-hot of Vivado, JEDI, and transformation of binary codes
into extended state codes). The LUT count is decreased by an average of 17.96 to 91.8%. Moreover, if some conditions are
met, the decrease in the LUT count is accompanied with a slight improvement in the operating frequency compared with
circuits based on extended state codes. The advantages of the proposed method multiply with increasing the numbers of
FSM inputs and states.
Keywords
Mealy FSM, FPGA, LUT, synthesis, extended state codes, combined state codes