International Journal of applied mathematics and computer science

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Paper details

Number 3 - September 2018
Volume 28 - 2018

Hardware reduction for LUT-based mealy FSMs

Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek

A method is proposed targeting a decrease in the number of LUTs in circuits of FPGA-based Mealy FSMs. The method improves hardware consumption for Mealy FSMs with the encoding of collections of output variables. The approach is based on constructing a partition for the set of internal states. Each state has two codes. It diminishes the number of arguments in input memory functions. An example of synthesis is given, along with results of investigations. The method targets rather complex FSMs, having more than 15 states.

Mealy FSM, synthesis, FPGA, LUT, partition, encoding collections of output variables