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Paper details
Number 3 - September 2022
Volume 32 - 2022
Improving the LUT count for Mealy FSMs with transformation of output collections
Alexander Barkalov, Larysa Titarenko, Małgorzata Mazurkiewicz
Abstract
A method is proposed which aims at reducing the number of LUTs in the circuits of FPGA-based Mealy finite state
machines (FSMs) with transformation of collections of outputs into state codes. The reduction is achieved due to the use
of two-component state codes. Such an approach allows reducing the number of state variables compared with FSMs
based on extended codes. There are exactly three levels of LUTs in the resulting FSM circuit. Each partial function is
represented by a single-LUT circuit. The proposed method is illustrated with an example of synthesis. The experiments
were conducted using standard benchmarks. They show that the proposed method produces FSM circuits with significantly
smaller LUT counts compared with those produced by other investigated methods (Auto and One-hot of Vivado, JEDI, and
transformation of output collection codes into extended state codes). The LUT count is decreased by, on average, from
9.86% to 59.64%. The improvement of the LUT count is accompanied by a slightly improved performance. The maximum
operating frequency is increased, on average, from 2.74% to 12.93%. The advantages of the proposed method become more
pronounced with increasing values of FSM inputs and state variables.
Keywords
Mealy FSM, FPGA, LUT, synthesis, state codes